Submicrometer InP/InGaAs DHBT Architecture Enhancements Targeting Reliability Improvements
Identifieur interne : 000448 ( Main/Repository ); précédent : 000447; suivant : 000449Submicrometer InP/InGaAs DHBT Architecture Enhancements Targeting Reliability Improvements
Auteurs : RBID : Pascal:13-0130297Descripteurs français
- Pascal (Inist)
- Transistor bipolaire hétérojonction, Fiabilité, Circuit intégré ultra rapide, Défaillance, Contrainte thermique, Contrainte électrique, Collecteur, Densité courant, Emetteur, Conception assistée, Jonction émetteur base, Résistance thermique, Autoéchauffement, Essai vieillissement accéléré, Phosphure d'indium, Composé binaire, Conception circuit, Comportement thermique, InP.
English descriptors
- KwdEn :
- Accelerated aging test, Base emitter junction, Binary compound, Circuit design, Collector, Computer aided design, Current density, Electric stress, Failures, Heterojunction bipolar transistors, Indium phosphide, Reliability, Self heating, Thermal behavior, Thermal resistance, Thermal stress, Transmitter, Very high speed integrated circuits.
Abstract
We report on the reliability of InP/InGaAs DHBTs used in very high speed ICs and present the analysis of HBT failure mechanisms after thermal and bias stresses (junction temperature from 87 °C to 240 °C, collector current density fixed at 400 kA/cm2, and collector-emitter voltage from 1.5 to 2.7 V). The physical origins of these failure mechanisms have been investigated using TCAD simulation. It points out the emitter sidewalls, the base-emitter junction periphery, and the emitter access resistance. Through three device generations, the analysis pointed out the successive technological enhancements to reduce the thermal resistance RTH and subsequently decrease the self-heating, leading to minimizing the impact of failure mechanisms.
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Kone</name><affiliation wicri:level="3"><inist:fA14 i1="01"><s1>Bordeaux University</s1><s2>33405 Talence</s2><s3>FRA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>11 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Aquitaine</region><settlement type="city">Talence</settlement></placeName></affiliation></author><author><name sortKey="Grandchamp, Brice" uniqKey="Grandchamp B">Brice Grandchamp</name><affiliation wicri:level="3"><inist:fA14 i1="01"><s1>Bordeaux University</s1><s2>33405 Talence</s2><s3>FRA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>11 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Aquitaine</region><settlement type="city">Talence</settlement></placeName></affiliation></author><author><name sortKey="Hainaut, Cyril" uniqKey="Hainaut C">Cyril Hainaut</name><affiliation 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University</s1><s2>33405 Talence</s2><s3>FRA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>11 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Aquitaine</region><settlement type="city">Talence</settlement></placeName></affiliation></author><author><name sortKey="Zimmer, Thomas" uniqKey="Zimmer T">Thomas Zimmer</name><affiliation wicri:level="3"><inist:fA14 i1="01"><s1>Bordeaux University</s1><s2>33405 Talence</s2><s3>FRA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>11 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Aquitaine</region><settlement type="city">Talence</settlement></placeName></affiliation></author><author><name sortKey="Nodjiadjim, Virginie" uniqKey="Nodjiadjim V">Virginie Nodjiadjim</name><affiliation wicri:level="3"><inist:fA14 i1="02"><s1>Alcatel- Thales III-V Laboratory</s1><s2>91461 Marcousis</s2><s3>FRA</s3><sZ>7 aut.</sZ><sZ>8 aut.</sZ><sZ>9 aut.</sZ><sZ>10 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Île-de-France</region><settlement type="city">Marcousis</settlement></placeName></affiliation></author><author><name sortKey="Riet, Muriel" uniqKey="Riet M">Muriel Riet</name><affiliation wicri:level="3"><inist:fA14 i1="02"><s1>Alcatel- Thales III-V Laboratory</s1><s2>91461 Marcousis</s2><s3>FRA</s3><sZ>7 aut.</sZ><sZ>8 aut.</sZ><sZ>9 aut.</sZ><sZ>10 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Île-de-France</region><settlement type="city">Marcousis</settlement></placeName></affiliation></author><author><name sortKey="Dupuy, Jean Yves" uniqKey="Dupuy J">Jean-Yves Dupuy</name><affiliation wicri:level="3"><inist:fA14 i1="02"><s1>Alcatel- Thales III-V Laboratory</s1><s2>91461 Marcousis</s2><s3>FRA</s3><sZ>7 aut.</sZ><sZ>8 aut.</sZ><sZ>9 aut.</sZ><sZ>10 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Île-de-France</region><settlement type="city">Marcousis</settlement></placeName></affiliation></author><author><name sortKey="Godin, Jean" uniqKey="Godin J">Jean Godin</name><affiliation wicri:level="3"><inist:fA14 i1="02"><s1>Alcatel- Thales III-V Laboratory</s1><s2>91461 Marcousis</s2><s3>FRA</s3><sZ>7 aut.</sZ><sZ>8 aut.</sZ><sZ>9 aut.</sZ><sZ>10 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Île-de-France</region><settlement type="city">Marcousis</settlement></placeName></affiliation></author><author><name sortKey="Maneux, Cristell" uniqKey="Maneux C">Cristell Maneux</name><affiliation wicri:level="3"><inist:fA14 i1="01"><s1>Bordeaux University</s1><s2>33405 Talence</s2><s3>FRA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>11 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Aquitaine</region><settlement type="city">Talence</settlement></placeName></affiliation></author></titleStmt><publicationStmt><idno type="inist">13-0130297</idno><date when="2013">2013</date><idno type="stanalyst">PASCAL 13-0130297 INIST</idno><idno type="RBID">Pascal:13-0130297</idno><idno type="wicri:Area/Main/Corpus">001055</idno><idno type="wicri:Area/Main/Repository">000448</idno></publicationStmt><seriesStmt><idno type="ISSN">0018-9383</idno><title level="j" type="abbreviated">IEEE trans. electron devices</title><title level="j" type="main">I.E.E.E. transactions on electron devices</title></seriesStmt></fileDesc><profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Accelerated aging test</term><term>Base emitter junction</term><term>Binary compound</term><term>Circuit design</term><term>Collector</term><term>Computer aided design</term><term>Current density</term><term>Electric stress</term><term>Failures</term><term>Heterojunction bipolar transistors</term><term>Indium phosphide</term><term>Reliability</term><term>Self heating</term><term>Thermal behavior</term><term>Thermal resistance</term><term>Thermal stress</term><term>Transmitter</term><term>Very high speed integrated circuits</term></keywords><keywords scheme="Pascal" xml:lang="fr"><term>Transistor bipolaire hétérojonction</term><term>Fiabilité</term><term>Circuit intégré ultra rapide</term><term>Défaillance</term><term>Contrainte thermique</term><term>Contrainte électrique</term><term>Collecteur</term><term>Densité courant</term><term>Emetteur</term><term>Conception assistée</term><term>Jonction émetteur base</term><term>Résistance thermique</term><term>Autoéchauffement</term><term>Essai vieillissement accéléré</term><term>Phosphure d'indium</term><term>Composé binaire</term><term>Conception circuit</term><term>Comportement thermique</term><term>InP</term></keywords></textClass></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">We report on the reliability of InP/InGaAs DHBTs used in very high speed ICs and present the analysis of HBT failure mechanisms after thermal and bias stresses (junction temperature from 87 °C to 240 °C, collector current density fixed at 400 kA/cm<sup>2</sup>, and collector-emitter voltage from 1.5 to 2.7 V). The physical origins of these failure mechanisms have been investigated using TCAD simulation. It points out the emitter sidewalls, the base-emitter junction periphery, and the emitter access resistance. Through three device generations, the analysis pointed out the successive technological enhancements to reduce the thermal resistance R<sub>TH</sub> and subsequently decrease the self-heating, leading to minimizing the impact of failure mechanisms.</div></front></TEI><inist><standard h6="B"><pA><fA01 i1="01" i2="1"><s0>0018-9383</s0></fA01><fA02 i1="01"><s0>IETDAI</s0></fA02><fA03 i2="1"><s0>IEEE trans. electron devices</s0></fA03><fA05><s2>60</s2></fA05><fA06><s2>3</s2></fA06><fA08 i1="01" i2="1" l="ENG"><s1>Submicrometer InP/InGaAs DHBT Architecture Enhancements Targeting Reliability Improvements</s1></fA08><fA11 i1="01" i2="1"><s1>KONE (Gilles A.)</s1></fA11><fA11 i1="02" i2="1"><s1>GRANDCHAMP (Brice)</s1></fA11><fA11 i1="03" i2="1"><s1>HAINAUT (Cyril)</s1></fA11><fA11 i1="04" i2="1"><s1>MARC (François)</s1></fA11><fA11 i1="05" i2="1"><s1>LABAT (Nathalie)</s1></fA11><fA11 i1="06" i2="1"><s1>ZIMMER (Thomas)</s1></fA11><fA11 i1="07" i2="1"><s1>NODJIADJIM (Virginie)</s1></fA11><fA11 i1="08" i2="1"><s1>RIET (Muriel)</s1></fA11><fA11 i1="09" i2="1"><s1>DUPUY (Jean-Yves)</s1></fA11><fA11 i1="10" i2="1"><s1>GODIN (Jean)</s1></fA11><fA11 i1="11" i2="1"><s1>MANEUX (Cristell)</s1></fA11><fA14 i1="01"><s1>Bordeaux University</s1><s2>33405 Talence</s2><s3>FRA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>6 aut.</sZ><sZ>11 aut.</sZ></fA14><fA14 i1="02"><s1>Alcatel- Thales III-V Laboratory</s1><s2>91461 Marcousis</s2><s3>FRA</s3><sZ>7 aut.</sZ><sZ>8 aut.</sZ><sZ>9 aut.</sZ><sZ>10 aut.</sZ></fA14><fA20><s1>1068-1074</s1></fA20><fA21><s1>2013</s1></fA21><fA23 i1="01"><s0>ENG</s0></fA23><fA43 i1="01"><s1>INIST</s1><s2>222F3</s2><s5>354000502443190250</s5></fA43><fA44><s0>0000</s0><s1>© 2013 INIST-CNRS. All rights reserved.</s1></fA44><fA45><s0>28 ref.</s0></fA45><fA47 i1="01" i2="1"><s0>13-0130297</s0></fA47><fA60><s1>P</s1></fA60><fA61><s0>A</s0></fA61><fA64 i1="01" i2="1"><s0>I.E.E.E. transactions on electron devices</s0></fA64><fA66 i1="01"><s0>USA</s0></fA66><fC01 i1="01" l="ENG"><s0>We report on the reliability of InP/InGaAs DHBTs used in very high speed ICs and present the analysis of HBT failure mechanisms after thermal and bias stresses (junction temperature from 87 °C to 240 °C, collector current density fixed at 400 kA/cm<sup>2</sup>, and collector-emitter voltage from 1.5 to 2.7 V). The physical origins of these failure mechanisms have been investigated using TCAD simulation. It points out the emitter sidewalls, the base-emitter junction periphery, and the emitter access resistance. Through three device generations, the analysis pointed out the successive technological enhancements to reduce the thermal resistance R<sub>TH</sub> and subsequently decrease the self-heating, leading to minimizing the impact of failure mechanisms.</s0></fC01><fC02 i1="01" i2="X"><s0>001D03F04</s0></fC02><fC02 i1="02" i2="X"><s0>001D03F06A</s0></fC02><fC03 i1="01" i2="3" l="FRE"><s0>Transistor bipolaire hétérojonction</s0><s5>01</s5></fC03><fC03 i1="01" i2="3" l="ENG"><s0>Heterojunction bipolar transistors</s0><s5>01</s5></fC03><fC03 i1="02" i2="X" l="FRE"><s0>Fiabilité</s0><s5>02</s5></fC03><fC03 i1="02" i2="X" l="ENG"><s0>Reliability</s0><s5>02</s5></fC03><fC03 i1="02" i2="X" l="SPA"><s0>Fiabilidad</s0><s5>02</s5></fC03><fC03 i1="03" i2="3" l="FRE"><s0>Circuit intégré ultra rapide</s0><s5>03</s5></fC03><fC03 i1="03" i2="3" l="ENG"><s0>Very high speed integrated circuits</s0><s5>03</s5></fC03><fC03 i1="04" i2="X" l="FRE"><s0>Défaillance</s0><s5>04</s5></fC03><fC03 i1="04" i2="X" l="ENG"><s0>Failures</s0><s5>04</s5></fC03><fC03 i1="04" i2="X" l="SPA"><s0>Fallo</s0><s5>04</s5></fC03><fC03 i1="05" i2="X" l="FRE"><s0>Contrainte thermique</s0><s5>05</s5></fC03><fC03 i1="05" i2="X" l="ENG"><s0>Thermal stress</s0><s5>05</s5></fC03><fC03 i1="05" i2="X" l="SPA"><s0>Tensión térmica</s0><s5>05</s5></fC03><fC03 i1="06" i2="X" l="FRE"><s0>Contrainte électrique</s0><s5>06</s5></fC03><fC03 i1="06" i2="X" l="ENG"><s0>Electric stress</s0><s5>06</s5></fC03><fC03 i1="06" i2="X" l="SPA"><s0>Tensión eléctrica</s0><s5>06</s5></fC03><fC03 i1="07" i2="X" l="FRE"><s0>Collecteur</s0><s5>07</s5></fC03><fC03 i1="07" i2="X" l="ENG"><s0>Collector</s0><s5>07</s5></fC03><fC03 i1="07" i2="X" l="SPA"><s0>Colector</s0><s5>07</s5></fC03><fC03 i1="08" i2="X" l="FRE"><s0>Densité courant</s0><s5>08</s5></fC03><fC03 i1="08" i2="X" l="ENG"><s0>Current density</s0><s5>08</s5></fC03><fC03 i1="08" i2="X" l="SPA"><s0>Densidad corriente</s0><s5>08</s5></fC03><fC03 i1="09" i2="X" l="FRE"><s0>Emetteur</s0><s5>09</s5></fC03><fC03 i1="09" i2="X" l="ENG"><s0>Transmitter</s0><s5>09</s5></fC03><fC03 i1="09" i2="X" l="SPA"><s0>Emisor</s0><s5>09</s5></fC03><fC03 i1="10" i2="X" l="FRE"><s0>Conception assistée</s0><s5>10</s5></fC03><fC03 i1="10" i2="X" l="ENG"><s0>Computer aided design</s0><s5>10</s5></fC03><fC03 i1="10" i2="X" l="SPA"><s0>Concepción asistida</s0><s5>10</s5></fC03><fC03 i1="11" i2="X" l="FRE"><s0>Jonction émetteur base</s0><s5>11</s5></fC03><fC03 i1="11" i2="X" l="ENG"><s0>Base emitter junction</s0><s5>11</s5></fC03><fC03 i1="11" i2="X" l="SPA"><s0>Unión emisor base</s0><s5>11</s5></fC03><fC03 i1="12" i2="X" l="FRE"><s0>Résistance thermique</s0><s5>12</s5></fC03><fC03 i1="12" i2="X" l="ENG"><s0>Thermal resistance</s0><s5>12</s5></fC03><fC03 i1="12" i2="X" l="SPA"><s0>Resistencia térmica</s0><s5>12</s5></fC03><fC03 i1="13" i2="X" l="FRE"><s0>Autoéchauffement</s0><s5>13</s5></fC03><fC03 i1="13" i2="X" l="ENG"><s0>Self heating</s0><s5>13</s5></fC03><fC03 i1="13" i2="X" l="SPA"><s0>Autocalentamiento</s0><s5>13</s5></fC03><fC03 i1="14" i2="X" l="FRE"><s0>Essai vieillissement accéléré</s0><s5>14</s5></fC03><fC03 i1="14" i2="X" l="ENG"><s0>Accelerated aging test</s0><s5>14</s5></fC03><fC03 i1="14" i2="X" l="SPA"><s0>Ensayo envejecimiento acelerado</s0><s5>14</s5></fC03><fC03 i1="15" i2="X" l="FRE"><s0>Phosphure d'indium</s0><s5>22</s5></fC03><fC03 i1="15" i2="X" l="ENG"><s0>Indium phosphide</s0><s5>22</s5></fC03><fC03 i1="15" i2="X" l="SPA"><s0>Indio fosfuro</s0><s5>22</s5></fC03><fC03 i1="16" i2="X" l="FRE"><s0>Composé binaire</s0><s5>23</s5></fC03><fC03 i1="16" i2="X" l="ENG"><s0>Binary compound</s0><s5>23</s5></fC03><fC03 i1="16" i2="X" l="SPA"><s0>Compuesto binario</s0><s5>23</s5></fC03><fC03 i1="17" i2="X" l="FRE"><s0>Conception circuit</s0><s5>46</s5></fC03><fC03 i1="17" i2="X" l="ENG"><s0>Circuit design</s0><s5>46</s5></fC03><fC03 i1="17" i2="X" l="SPA"><s0>Diseño circuito</s0><s5>46</s5></fC03><fC03 i1="18" i2="X" l="FRE"><s0>Comportement thermique</s0><s5>47</s5></fC03><fC03 i1="18" i2="X" l="ENG"><s0>Thermal behavior</s0><s5>47</s5></fC03><fC03 i1="18" i2="X" l="SPA"><s0>Comportamiento térmico</s0><s5>47</s5></fC03><fC03 i1="19" i2="X" l="FRE"><s0>InP</s0><s4>INC</s4><s5>82</s5></fC03><fC07 i1="01" i2="X" l="FRE"><s0>Composé III-V</s0><s5>15</s5></fC07><fC07 i1="01" i2="X" l="ENG"><s0>III-V compound</s0><s5>15</s5></fC07><fC07 i1="01" i2="X" l="SPA"><s0>Compuesto III-V</s0><s5>15</s5></fC07><fN21><s1>105</s1></fN21><fN44 i1="01"><s1>OTO</s1></fN44><fN82><s1>OTO</s1></fN82></pA></standard></inist></record>Pour manipuler ce document sous Unix (Dilib)
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